Interconnect structure for electronic devices

ABSTRACT

A display device and method of fabricating the same. The display device comprises a first array of transparent conductors. The first array of transparent conductors has a first pitch defined by a first distance between adjacent transparent conductors of the first array of transparent conductors. The display device further comprises a second array of conductors disposed on a plurality of integrated circuit (IC) devices coupled to a carrier, which couples to the display device. The second array of conductors has a second pitch defined by a second distance between adjacent conductors of the second array of conductors. The first pitch and the second pitch are substantially similar. The first array of transparent conductors interconnects the second array of conductors.

FIELD OF THE INVENTION

[0001] The present invention relates to interconnect structures forelectronic devices, and more particularly, in certain embodiments, todisplay devices such as flat panel displays.

BACKGROUND OF THE INVENTION

[0002] While the present invention has many aspects and embodiments,this section will focus on those aspects which relate to displaydevices. While there are a large number of various different types ofdisplay devices, one very common display device utilizes pixelelectrodes to control a display medium such as a liquid crystal display(LCD) layer in order to create an image. These pixel electrodes maycontrol other types of display media such as electrophoretic displaymedia, organic light emitting diodes (OLED), or a polymer light emittingdiode (PLED). Typically, a pixel electrode works by creating locally anelectric field relative to another electrode. A display medium issandwiched between the two electrodes and reacts to this electric field.Well known examples of such types of displays are the active matrixliquid crystal displays used in modem laptop computers and passivematrix display used in modern PDA computers or cellular phones.

[0003]FIG. 1 illustrates an example of a backplane for an active matrixdisplay in the prior art. As is well known, a plurality of pixelelectrodes, such as pixel electrode 9C, are arranged in an array of rowsand columns. Each row of pixel electrodes is controlled by a rowelectrode such as row electrodes 2, 3, and 4. At least one transistordevice is coupled to each pixel electrode in order to control theupdating of new data to the pixel electrode in order to change the imagebeing displayed. For example, as shown in FIG. 1, the field effecttransistor (FET) 9A couples the pixel electrode 9C to the data line 1 oncolumn 5 when row 2 receives a high voltage signal (e.g. 5 volts),causing the data value provided on column 5 to be stored onto thecapacitor 9B which in turn causes the storage of a voltage value on thepixel electrode 9C. As is known in the art, each row receives aplurality of data in parallel substantially simultaneously as each row'ssignal line goes high, causing the gate electrode to allow thetransistor device to conduct, thereby causing the data from theassociated column to be written to the pixel electrode through thecapacitor. It will be appreciated in certain embodiments that thecapacitor is merely optional and the capacitance of the FET deviceitself will be sufficient to store the charge for the pixel electrode tothereby maintain the pixel electrode at a certain voltage. Thus thedisplay is updated one row at a time where each row receives in parallela plurality of data from the parallel columns, such as columns 5, 6, 7and column 8 as shown in FIG. 1. It will be appreciated that each pixelcell includes a display driver such as display drivers 9, 10, and 11which control associated pixel electrodes in the display shown in FIG.1.

[0004]FIG. 2 illustrates an example of a conventional passive matrixdisplay. A passive matrix display is similar to the active matrixdisplay except that each row and column is controlled by one driverattached to that row or column. A conventional passive matrix 100 is aliquid crystal display passive matrix comprising a number of layers. Thedisplay comprises a top substrate 102 and a bottom substrate 103. Thetop substrate 102 and the bottom substrate 103 can be made out of glass.Each of the top substrate 102 and the bottom substrate 103 is coatedwith a plurality of transparent conductive lines arranged in an array ofrows 104 or column 106. The rows 104 and the columns 106 are made out ofa highly transparent material, typically, indium tin oxide (ITO) toprevent the conductors from interfering with the image quality. As wellunderstood, the rows and columns of the transparent conductors operateas a grid of row and column of pixel electrodes, which passes thecurrent needed to activate the screen elements and control the pixels onthe display screen. On top of each of the transparent conductors, analignment layer 108 may be deposited. The alignment layer is typically apolymer material that has a series of parallel grooves running across itto help align the liquid crystal molecules in the appropriate direction,and to provide a base on which the molecules are attached. Spacer beads110 may also be disposed between the two alignment layers 108. Thespacer beads 110 help maintain a uniform distance between the twosubstrates 102 and 103 when they are placed together.

[0005] The edges are then sealed with an epoxy, but with a gap left inone corner. The corner allows liquid-crystal materials 111 to beinjected between the sheets (in a vacuum) before the plates are sealedcompletely. Next, polarizing layers 112, which are linear light filters,are applied to the outer-most surfaces of each of the substrate 102 and103. The polarizing layer 112 are arranged to match the orientation ofthe alignment layers 108. A backlight (not shown) can also be added,typically in the form of cold-cathode fluorescent tubes mounted alongthe top and bottom edges of the panel, the light from these beingdistributed across the panel using a plastic light guide or prism.

[0006]FIG. 3 illustrates the passive display 100 driven by a row driver114 and a column driver 116. This figure shows that an image 120 isformed when the row driver 114 and the column drive 117 passes signalsalong the corresponding row 106 and column 104 of the display 100. Thecolumn driver 116 and the row driver 114 are typically integratedcircuits containing input/output circuit elements that are customarilyfabricated upon semiconductor (silicon) chips to drive the display 100.The integrated circuits typically include the transistor, resistor andcapacitor elements required to perform the circuit function (e.g.,diving the display). The column driver 116 and the row driver 114 can beintegrated into the substrate of the display, e.g, chip-on-glass (COG),or fabricated on a package that is attached to the display, e.g.,chip-on-flex (COF) or tape automated bonded (TAB).

[0007] While the foregoing display architecture works well generally formany types of applications, it is well known that manufacturing thesedisplays is expensive due to poor yields especially when the size of thedisplay is large. It is also well known that to save cost, the siliconused to make the display drivers (e.g., drivers for a passive matrixdisplay), are fabricated to be as small as possible. One problem withthis cost saving approach is that the driver interconnections to thedisplay become extremely complex and unreliable which, further hindershigh yield.

[0008]FIG. 4 illustrates that a substrate of the display 100 has a pitchP3 wherein the pitch is defined as the distance between two adjacentlines of display conductors (e.g., the distance between conductor row104 and conductor row 105). Usually, lines of conductor have a certainwidth, then the pitch is defined by the distance between the middle ofone line to the middle of the other line. A carrier 120 including thedriver chip 114 is shown to connect to the display 100. The driver 114is fabricated from a small piece of silicon to minimize the cost of thedisplay. Because of the size reduction, the IC driver 114 has a padpitch P1 that is substantially smaller than the pitch P3, (a pad pitchon an IC is defined as the distance between the middle of a pad and themiddle of an adjacent pad). Pitch P2, which is the interconnection pitchdirectly at the edge of the carrier 120 to the display, may be as largeas the pitch P3. However, the complex interconnection leads from thedriver 114 to the carrier 120 still remains the problem. This leads topoor yield problems. For example, though not shown in FIG. 4, inactuality, the routing is much more complex, especially when thedisplay's arrays of conductors comprise many more conductors. Forexample, a typical display has a line pitch of about 80-400 μm and thedriver has a pad pitch of about 40-60 μm. Beside the IC interconnectionpoor yield, this approach necessitates complex and long routing lines,leading to signal integrity damages for demanding high voltage or highcurrent optical media. These problems escalate for the case of highresolution displays where the pitch of the arrays of conductors is muchsmaller.

[0009] With recent demands for higher resolution displays, the pitch ofthese displays are smaller since more rows and columns of conductors areemployed to enhance the resolution. The increase in density of theconductors in the display magnifies the problem of complexinterconnection from the driver to the display making the fabrication ofthe display complicated and costly.

[0010]FIG. 5 illustrates that to minimize the drastic difference in thepitch between the display and the driver, two drivers have been used todrive a display panel. The display 100 connects to a carrier 120 havinga driver 114 on one side and to a carrier 122 having a driver 115 on theother side. This is typically referred to as odd/even double-sidedconnection. The display has a pitch P3 which is defined by the distancebetween two adjacent rows of conductors (e.g., the distance betweenconductor row 104 and conductor row 105). The driver 114 of FIG. 5 has apitch P1 which is still smaller than P3 but is about two times largerthan the driver 114 illustrated in FIG. 4 above. The pitch of theconnection along the carrier 120 and 122 may be larger than the pitch ofthe display 100. This may minimize the complex interconnection problemseen in the example of FIG. 4 but the silicon material requirement orsurface has doubled. Moreover, the double-side interconnection alsoreduces the compactness for the display making it difficult to fabricatesmall display devices (useful for portable application: cell phone,laptop . . . ).

[0011] In all of the examples discussed above, most of the time the ICdrivers only interface to the display 100 only from one side of thechip. Because not all sides of the chips are utilized to interconnectwith the display lines, this results in wasting costly material such assilicon thus driving up the cost of fabricating the display.

[0012] It is thus desirable and advantageous to make a more simple, costeffective, and reliable interconnection structure for used withelectronic devices such as flat panel displays.

SUMMARY OF THE INVENTION

[0013] Various different aspects and embodiments of different inventionsare described here. These different aspects include differentconfigurations of display devices as well as methods relating to thefabrication of the display devices.

[0014] According to one aspect of the present invention, a displaydevice comprises a first array of transparent conductors. The firstarray of transparent conductors has a first pitch defined by a firstdistance between adjacent transparent conductors of the first array oftransparent conductors. The display device further comprises a secondarray of conductors disposed on a plurality of integrated circuit (IC)devices which are coupled to a carrier, which couples to the displaydevice. The second array of conductors has a second pitch defined by asecond distance between adjacent conductors of the second array ofconductors. The first pitch and the second pitch are substantiallysimilar. The first array of transparent conductors interconnects thesecond array of conductors.

[0015] According to another aspect of the invention, a display devicecomprises a top substrate having a first length and a first array oftransparent conductors. The display device further comprises a bottomsubstrate having the first length and a second array of transparentconductors. A first carrier coupling to the top substrate and a secondcarrier coupling to the bottom substrate. Each of the first carrier andthe second carrier has a second length, includes a plurality of ICdevices, and includes carrier conducting pads to interconnect theplurality of IC devices to the transparent conductors. Each of theplurality of IC device has an array of interconnections whichsubstantially surround a perimeter of each of the plurality of ICdevices.

[0016] According to another aspect of the present invention, a displaydevice comprises a top substrate having a first array of transparentconductors. The display device also comprises a bottom substrate havinga second array of transparent conductors. A first plurality of ICdevices and a second plurality of IC devices are fabricated onto one ofthe top substrate or the bottom substrate. A crossover contact area isextended from the top substrate or the bottom substrate which has thefirst plurality of IC devices fabricated therein. The crossover contactarea includes a plurality of contact conductors which interconnect thesecond plurality of IC devices to one of the top substrate and thebottom second substrate which does not have the first plurality of ICdevices and the second plurality of the IC devices fabricated therein.

[0017] According to yet another aspect of the present invention, adevice for use with a display comprises a substrate. The substratecomprises a plurality of IC devices deposited therein. The substratefurther comprises double-layer structure conductors which comprise afirst set of conductors and a second set of conductors separated by aninsulation layer. The insulation layer has a plurality of contact viasforming therethrough. A plurality of conducting pads locating on asurface of each of the plurality of the IC devices. The plurality ofconducting pads interconnects with one of the first set of conductors orthe second set of conductors through the first plurality of contactvias. The first set of conductors and the second set of conductorsinterconnect with each other through the plurality of contact vias. And,the first set of conductors and the second set of conductorsinterconnect with an array of transparent conductors in the displaydevices.

[0018] Other aspects and methods are also described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements.

[0020]FIG. 1 illustrates an example of a prior art active-matrixdisplay.

[0021]FIG. 2 illustrates an example of a prior art passive-matrixdisplay.

[0022]FIG. 3 illustrates an example of a prior art passive-matrixdisplay having two substrates each having a driver (e.g., a row driverand a column driver).

[0023]FIG. 4 illustrates a top view of an interconnection problemassociated with the prior art display.

[0024]FIG. 5 illustrates yet another top view of an interconnectionproblem associated with the prior art display.

[0025]FIG. 6 illustrates an exemplary embodiment of a display accordingto one aspect of the present invention in which IC devices interconnectfrom more than one sides of each of the IC devices.

[0026]FIG. 7 illustrates an exemplary embodiment of a display accordingto another aspect of the present invention in which IC devices areincorporated into carriers which are coupled to display substrates ofthe display.

[0027]FIG. 8 illustrates a top view of a carrier that can be used insome exemplary embodiments of the present invention.

[0028]FIG. 9 illustrates a cross-sectional view of a carrier that can beused in some exemplary embodiments of the present invention.

[0029]FIG. 10A illustrates a three-dimensional view of a carrier thatcan be used in some exemplary embodiments of the present invention whichincludes IC devices making interconnections from all sides of each ofthe IC devices and the carrier facilitating interconnections from morethan one side of the carrier.

[0030]FIG. 10B illustrates a three-dimensional view of a carrier similarto FIG. 10A except that the carrier facilitates interconnections fromonly one side of the carrier.

[0031]FIG. 11 illustrates an exemplary carrier that can be used in someexemplary embodiments of the present invention.

[0032]FIG. 12 illustrates an exemplary embodiment of an IC device whichincludes contact pads according to one aspect of the present invention.

[0033]FIG. 13 illustrates an exemplary advantage of some of theexemplary embodiments made according to the present invention in whichthe pitch of IC chip to the carrier is similar to the pitch of thedisplay.

[0034]FIG. 14 illustrates an exemplary embodiment of a display accordingto another aspect of the present invention in which display drivers areintegrated into the display panel.

[0035]FIGS. 15A and 15B illustrate cross-sectional views of exemplaryembodiments of a structure of double conductive layers that can be usedto drive a display made according to some aspects of the presentinvention.

[0036]FIG. 16 illustrates a top view of another exemplary embodiment ofa structure of double conductive layers that can be used to drive adisplay made according to some aspects of the present invention.

[0037]FIG. 17 illustrates a three-dimensional view of the embodimentshown in FIG. 16.

[0038]FIG. 18A illustrates a top view and FIG. 18B illustrate across-sectional view of yet another exemplary embodiment of a structureof double conductive layers that can be used to drive a display madeaccording to some aspects of the present invention.

[0039]FIG. 19A illustrates an exploded view of the embodiment shown inFIGS. 18A and 18B.

[0040]FIG. 19B illustrates a cross-sectional view of double-layerstructure conductors.

[0041]FIGS. 20A illustrates a top view and FIG. 20B illustrate across-sectional view of yet another exemplary embodiment of a structureof double conductive layers that can be used to drive a display madeaccording to some aspects of the present invention.

[0042]FIGS. 21A, 21B, and 21C illustrate another exemplary embodiment ofa display according to an aspect of the present invention in which boththe row drivers and the column drivers are incorporated in one of thetwo substrates of the display.

[0043]FIG. 22A and 22B illustrate yet another exemplary embodiment of adisplay according to an aspect of the present invention in which boththe row drivers and the column drivers are embedded in a carrier whichis coupled to one of the two substrates of the display.

DETAILED DESCRIPTION

[0044] The subject invention will be described with reference tonumerous details set forth below and the accompanying drawings, whichwill illustrate the invention. The following description and drawingsare illustrative of the invention and are not to be construed aslimiting the invention. Numerous specific details are described toprovide a thorough understanding of the present invention. However, incertain instances, well-known or conventional details are not describedin order to not unnecessarily obscure the present invention in detail.Further, various aspects of the present invention will be described withreference to the use of aspects and embodiments of the invention indisplay systems. It will be appreciated that the reference to displaysystems is merely for purposes of illustration and are not to beconstrued as limiting the invention.

[0045] In the numerous exemplary embodiments below, an interconnectstructure for a display is disclosed. In general, the interconnectstructure includes a first array of transparent conductors. The firstarray of transparent conductors has a first pitch defined by a firstdistance between adjacent transparent conductors or more precisely, adistance between the middle of each adjacent lines of the first array oftransparent conductors. A second array of conductors is disposed on aplurality of integrated circuit devices which are coupled to a carrier.The carrier is coupled to the display device. The second array ofconductors has a second pitch which is defined by a second distancebetween adjacent conductors of the second array of conductors. In thisembodiment, the first pitch and the second pitch are substantiallysimilar.

[0046]FIG. 6 illustrates an exemplary embodiment of a display 200according to one aspect of the present invention. The display 200 can bea column and row driven display (e.g., a passive matrix display). Thedisplay 200 comprises a substrate 202 in which a display area 201 isdefined. An array of transparent conductors 212 (e.g., ITO) is depositedon the substrate 202 to cover at least all of the display area 201 usingconventional methods. The substrate 202 is also referred to as a displaypanel. The substrate 202 having the transparent conductors 212 alreadyformed therein can also be obtained commercially from numeroussuppliers. For example, from CPFilms, Canoga Park Calif. or NEOVAC,Santa Rosa Calif. FIG. 6 shows that the array of the transparentconductors 212 can be arranged in an array of rows of conductors. Acarrier 206 having a plurality of integrated circuit (IC) devices 210for driving the display 200 is coupled to the substrate 202.

[0047] The substrate 202 can be made out of transparent material such asglass or plastic or any other suitable material for making a display. Ina preferred embodiment, the substrate 202 is made out of a flexiblematerial suitable for used in a flat panel display.

[0048] Each of the plurality of the IC devices 210 comprises circuitsthat perform particular functions relating to driving the display 200(see below discussion). Each of the IC devices also comprises a firstplurality of connection pads 214 to connect the IC devices to thecorresponding conductors in the array 212. The connection pads 214interconnect to the array 212 through a second plurality of connectionpads 216 present on the carrier 206. Each of the connection pads 216couple to an interconnection line 218 which is coupled to one of therows of the conductors in the array 212. In most instances, theinterconnection lines 218 are the same lines as the array of conductors212. In a preferred embodiment, the second plurality of connections pads216 are aligned along the long edges of the carrier 206 for ease ofconnecting carrier comprising the IC devices to the display. In otherembodiments, the second plurality of connection pads 216 is alignedalong one long edge of the carrier 206. The connection pads 216 can bemade out of conductive material (e.g., metals, aluminum, gold, silver,and copper, etc.). The connection pads 214 are also made out of someconductive material. The connection pads 214 are formed on the topsurface of each of the IC devices 210 (see discussion in FIG. 12). Theinterconnection lines 218 can be a set of conductive lines (e.g.,metals, aluminum, gold, silver, and copper, etc.) or can be the same ITOlines 212. A method such as photolithography can be used to form theselines 218 to connect the connection pads 216 to the appropriateconductors 212.

[0049] As shown in FIG. 6, the display 200 has a first pitch 220, whichis the pitch of the display. The first pitch 220 is defined by a firstdistance which is the distance between (middle of) adjacent transparentconductors of the array of transparent conductors 212 (e.g., conductors212 a and 212 b). The pitch 220 depends on the resolution desired forthe particular display. In one example, the display 200 has a pitch of200 μm. The carrier 206 has a second pitch 222 which is the pitch of theconnection pads 216. In one example, the pitch 222 is equal to the pitch220. In another example, the pitch 222 is substantially similar to thepitch 220. For instance, when the first pitch 220 is about 200 μm, thesecond pitch 222 is also about 200 μm. Alternatively, the second pitch222 may vary from 150 μm to 250 μm which makes the second pitch 222substantially similar to the first pitch 220.

[0050] Also as shown in FIG. 6, the display 200 has a first length L1(the length of the interconnecting side). The carrier 206 has a secondlength L2. In a preferred embodiment, the first length L1 and the secondlength L2 are substantially similar. For example, when the first lengthL1 is about 20 cm, the second length L2 is also about 20 cm.

[0051]FIG. 7 illustrates another exemplary embodiment of a display 300which similar to the display 200. The display 300 can be a flat paneldisplay. The display 300 includes both the row and column driven layers.The display 300 comprises a top substrate 202 and a bottom substrate204. Each of the top substrate 202 and the bottom substrate 204 issimilar to the one discussed in FIG. 6. Each of the top substrate 202and the bottom substrate 204 can also be referred as a display panel.The top substrate 202 is shown to include an array of columns oftransparent conductors 212. The bottom substrate 204 includes an arrayof rows of transparent conductors 212. The top substrate 202 alsoincludes a carrier 206 and the bottom substrate 204 includes a carrier208. The carrier 206 and the carrier 208 of FIG. 7 are similar to thecarrier 206 shown in FIG. 6. The display 300 has a display area which isdefined by an area of the display 300 that does not have the carriers206 and the carrier 208 coupled thereto. A display medium, for example,LCD, PLED, and OLED, is deposited between the top substrate 202 and thebottom substrate 204 over the display area according to conventionalmethods (not shown).

[0052] In one exemplary embodiment, the carrier 206 of FIG. 7 is coupledto the top substrate 202 through an electrically conductive adhesivematerial (not shown). The carrier 204 of FIG. 7 is coupled to the bottomsubstrate 204 also through an electrically conductive adhesive material(not shown). One example of an electrically conductive adhesive that canbe used to couple the carriers to the substrates is an anisotropicconductive polymer. The anisotropic conductive polymer offers structuralintegrity as well as electrical interconnection for the second pluralityof connection pads 216 (shown in FIG. 6) to the transparent conductorson the substrates. The anisotropic conductive polymer allows electricalcurrent to travel uni-directionally, usually only along the Z-direction(or the thickness) of the conductive adhesive. The anisotropicconductive polymer used for this purpose can be supplied in the form ofa heat-curable liquid/paste or a heat curable thermosetting orthermoplastic adhesive film otherwise known as anisotropic conductivefilm (ACF). The ACF is preferred for coupling the IC devices to asubstrate of the present invention.

[0053]FIG. 8 illustrates a topical view of an exemplary embodiment of acarrier 400 such as the carrier 206 and 208 discussed above. The carrier400 comprises a plurality of IC devices 210; each of the IC devices 210includes a first plurality of connection pads such as the connectionspads 214 shown in FIG. 6. The first plurality of connections padsinterconnect the IC device 210 to a second plurality of connection padsthat are designated as output pads 216 shown in FIG. 8, and a secondplurality of connection pads that are designated as input pads 226 alsoshown in FIG. 8. The output pads 216 sends appropriate signals totransparent electrodes on the display such as the transparent conductors(e.g., transparent conductors in the array 212 of FIG. 6 and 7). Theinput pads 226 receive data and instruction signals from an outsideelectronic device (for instance an IC microcontroller) to the IC devices210 such as power, data, clock, and ground.

[0054] In one example, the IC devices 210 are designed such theinterconnections made from each of the IC devices 210 substantiallysurround a perimeter of this IC device 210. FIG. 8 shows that each ofthe IC devices 210 makes interconnections from more than one of itssides. In another example, the interconnections made from each of the ICdevices 210 substantially surround a perimeter of the carrier 400. Inthis example, the output pads 216 and the input pads 226 can be alignedalong the edges of the carrier 400. FIG. 8 shows that the output pads216 and the input pads 226 are aligned along two edges of the carrier400. It is to be understood that the alignment of the output pads 216and the input pads 226 is not limited to these two edges of the carrier400. Also, the alignment of the output pads 216 and the input pads 226may only occupy one edge of the carrier 400. Additionally, anycombinations of long and short edges locations are possible for inputand output pads.

[0055] An ACF tape 224 is placed along the edges of the carrier 400 overthe areas where the connection pads 216 and 226 are located usingconventional methods of applying an ACF tape. Pressures may be used tofacilitate the placing of the ACF tape 224 over these areas.Alternatively, the ACF tape 224 can be applied only to output pads 216,then the input pads are connected directly to the outside electronicdevice (on a printed circuit board for instance) by traditionalinterconnecting methods: solder, silver-epoxy, ACF, heat-seal, etc.

[0056]FIG. 9 illustrates a cross-sectional view of a display 200 havingthe carrier 400 coupling to a display substrate 228. The displaysubstrate 228 can be the top substrate 202 or bottom substrate 204 shownin FIG. 7. The substrate 228 includes an array of transparent conductors230 which may be a row or column of conductors. The substrate 228 iscoupled to the carrier 400 having the plurality of IC devices 210deposited therein. Similar to discussed above, each of the IC devices210 has connection pads (not shown) and the carrier has output pads 216and input pads 226 (not shown). These pads facilitate interconnectionsfrom the IC devices to the transparent conductors 230. The ACF tape 224on the carrier 400 couples to the display substrate 228 such that it isin direct contact with the transparent conductors 230 on the substrate228.

[0057] In another embodiment, to prevent shorting to the IC devices, aninsulation layer 231 is coated over the entire surface of the carrier400 having the IC devices 210 embedded therein. Contact vias are formedin the insulation layer over those areas where the connection pads (notshown) on the IC devices 210 exist. In one example, the contact vias areonly formed over the areas of those connection pads that electricalinterconnections are necessary. Thus, the contact vias are formed wherethe interconnections will be made to the IC devices 210. A layer ofmetal connector 232 is deposited over the insulation layer. The metalconnector 232 interconnects the IC devices 210 to the second connectionpads (not shown) along the edges of the carrier 400. In one example, themetal connector 232 makes up the only metal layer in the carrier 400. Assuch, the carrier 400 can be referred as a single-metal structureconnector. The insulation layer 231 prevents shorting to the IC devices210 by allowing electrical interconnection only through the vias; otherplaces on the IC devices not dedicated to connecting to outside of theIC devices are not affected by the interconnection.

[0058]FIG. 10A illustrates a three-dimensional view of another exemplarydisplay 200 of the present invention. In this embodiment, the carrier400 discussed above is attached to the display substrate 228. Thisfigure shows that each of the IC devices 210 in the carrier 400 hasinterconnection made from more than one of its sides. Each of the ICdevices 210 has a first plurality of connection pads (not shown) placedon the surface of the IC device 210 in a way interconnections made fromthe IC device 210 can be made from more than one sides as shown in thisfigure. The first plural connection pads further interconnect to asecond plurality of second connection pads 216 through conductive lines.In one example, the second plurality of connection pads 216 is placedalong the edges of the carrier 400. The second plurality of connectionpads 216 are placed along at least two of the four edges of the carrier400. In another example, the second plurality of connection pads 216 areplaced along only one edge of the carrier 400 as illustrated in FIG.10B.

[0059] In another embodiment, the carrier 400 includes an extension400-x (see FIGS. 10A and 10B). The extension 400-x includes a pluralityof input pads 217 which interconnects the carrier 400 to outsideelectronics.

[0060]FIGS. 10A and 10B show that the carrier 400 is coupled to thedisplay substrate 228. In one example, the carrier 400 is coupled to thedisplay substrate 228 using the ACF tape shown discussed above. The ACFenables both mechanical adhesion and electrical contacts between thecarrier 400 and the display substrate 228. When the carrier 400 isattached to the display substrate 228 the second plurality of connectionpads 216 couple to the array of transparent conductors 230 as shown inFIG. 10A. In one embodiment, the second plurality of connection pads 216interconnects to the transparent conductors 230 from at least one of thelong edge of the carrier 400 as shown in FIG. 10B. Interconnections frommore than one side of the IC devices 210 as well as more than one edgeof the carrier is one reason that the carrier 400 has a pitch that issubstantially similarly to the pitch of the display substrate 228. Inanother embodiment, the second plurality of conductive pad 216interconnects to the transparent conductors 230 from two long edges ofthe carrier 400 as shown in FIG. 10A. Although not shown, theinterconnect can also be made from all sides of the carrier 400.

[0061]FIG. 11 illustrates an exemplary embodiment of the carrier 400mentioned above. The carrier 400 can be made out of a flexible or rigidmaterial which can be opaque or transparent. In a preferred embodiment,the carrier 400 is flexible. A flexible carrier 400 allows for aroll-to-toll fabrication and for easier stored in rolls afterfabrication process. The carrier 400 can also be a rigid web, and ifmade thin enough, can be rolled up for convenient storage. The carrier400 can be made out of a silicon wafer material, a gallium arsenidewafer, a ceramic material, plastic, glass, silica, or any suitablesubstrate used in semiconductor field. The carrier 400 can also be madeout of a transparent material.

[0062] The carrier 400 in FIG. 11 includes a plurality of receptor sites242, each of which is designed to couple to an IC device 210. Thereceptor sites 242 can be created into the carrier 400 using techniquessuch as stamping, embossing, injection molding, casting among others.The exemplary embodiment illustrated in this figure depicts that thereceptor sites 242 are recessed regions created into the surface of thecarrier 400. Having receptor sites 242 being recessed is not alimitation of the present invention. If the carrier 400 is an organicmaterial and is an amorphous or semicrystalline polymer, the receptorsites may be embossed into the polymer material with a mold that matchesthe block size and pitch for the device being produced (e.g., an activematrix LCD). The receptor sites can be molded or carved into a surface,or, be designed as a raised area of a substrate. The receptor sites 242can be recesses, bosses, protrusions, bulges, or protuberances. Thereceptor sites 242 thus need not be a recessed region in the carrier400.

[0063] Continuing with FIG. 11, the carrier 400 includes a plurality ofIC devices 210 deposited in the receptor sites 242. In a preferredembodiment, each of the IC devices 210 has a trapezoidal shape having asurface that includes four sides. Each of the receptor sites 242 alsohas a trapezoidal shape complimentary to the shape of the IC devices210. The dimensions of the receptor sites 242 and the IC devices 210 arealso similar. The trapezoidal shape of the IC devices 210 and thereceptor sites 242 facilitate the correct alignment of the IC devices210 into the carrier 400. These similarities (in shape and size) helpthe receptor sites 242 to easily mate with the IC devices 210.

[0064] It will be appreciated that the IC devices 210 and the receptorsites 242 may have other shapes, for instance, a cylindrical shape,pyramid shape, rectangular shape, square shape, T-shape, kidney shape,or the like. Even with other shapes, the IC devices 210 and the receptorsites 242 have similar shapes and dimensions for good mating.

[0065] The IC devices can be deposited into the receptor sites 242 usingany conventional method such as pick-and-place or fluid-self-assembly(FSA) or the combination thereof. In the preferred embodiment, the ICdevices 210 are deposited into the carrier 400 using FSA. Fluidicself-assembly is known in the art; see, for example, U.S. Pat. No.5,545,291 which is hereby incorporated herein by reference. In the FSAapproach, IC devices 210 can be coupled to the receptor sites 242 bybeing flown over the carrier 400 in a slurry solution (not shown).

[0066] Continuing with FIG. 11, the carrier 400 having IC devices 210deposited therein also includes an insulation layer 246 deposited overthe carrier 400 and the IC devices 210. The insulation layer 246 is adielectric material that can be selected from a group of polyimide,epoxy, photo imageable solder mask or permanent photoresists. In oneexample, the insulation layer 246 is made out of silicon dioxide. Theinsulation layer 246 can function as a planarization layer that sealsthe IC devices 210 to the carrier 400 and creates a flat surface for thecarrier 400 after the IC devices are deposited in the carrier 400. Theinsulation layer 246 also has a plurality of contact vias 244. Thecontact vias 244 are holes in the insulation layer 246 through whichelectrical interconnections to and from the IC devices can beestablished. The carrier 400 includes a metal conductor layer 248deposited on top of the insulation layer 246. The metal conductor layer248 facilitates the necessary electrical interconnections to and fromthe IC devices 210. In one example, the metal conductor layer 248 ispatterned such that it matches the array of transparent conductors(e.g., array of transparent conductors 212) of the display substratethat the carrier 400 is to be coupled to.

[0067]FIG. 12 illustrates in details an IC device 210. In general, theIC device 210 includes semiconductors that are manufactured on siliconwafers. Alternatively, the IC devices can be a functional microstructureor a micro-scale electronic device such as a NanoBlock™ made by AlienTechnology Inc., Morgan Hill, Calif. These functional microstructurescan also be the micro structure that have been invented and disclosed inU.S. Pat. No. 6,291,896 entitled “Functionally Symmetric IntegratedCircuit Die” which was filed Feb. 16, 1999 by the inventor John StephenSmith. This application is hereby incorporated herein by reference.Methods for forming the separated integrated circuits are also describedin co-pending U.S. patent application Ser. No. 09/433,605, entitled“Methods for Creating Elements of Predetermined Shape and Apparatusesfor Using these Elements” which was filed on Nov. 2, 1999. Thisapplication is hereby incorporated herein by reference.

[0068]FIG. 12 shows an example of an integrated circuit 190 according toone embodiment of the present invention. This circuit 190 may be used tocreate the IC devices 210 shown in FIGS. 6 to 11. It may be fabricatedsuch that internally it is asymmetric but externally its electricalinterface pads are arranged so that they are externally functionallysymmetric. However, according to other aspects of the invention, anembodiment of the circuit 190 does not need to be functionally symmetricexternally.

[0069] The circuit 190 includes the microcontroller 191 which isoptionally coupled to position detector logic 208. The microcontroller191 is also coupled to a control bus 204 and may optionally be coupledto a data bus 205. Four drivers 200, 201, 202 and 203 are coupled to thedata bus 205 and are also coupled to the control bus 204. Each driver iscoupled to its respective I/O (input/output) pad on the IC device andthey are also coupled to their respective pads for outputs as shown inFIG. 12. For example, driver 200 is coupled to pad I/O 4 labeled as pad196. It will be appreciated that this is an external electricalinterface pad on the integrated circuit. The driver 200 is also coupledto the pads 192 which in this case are two output pads 4A and 4B.Examples of pads 192 are connection pads 214 shown in FIG. 6.

[0070] An input/output pad can be a configurable pad which isconfigurable to be either an input pad or an output pad or ano-operation pad depending upon control signals provided to theparticular driver. In one embodiment, these control signals may comefrom the control bus 204. In another embodiment, the control signals maycome from the control signal logic 209 which is coupled to each of thedrivers 200, 201, 202, and 203. Control signal logic 209 receivessignals from the position detector logic 208 which indicates theposition of the integrated circuit 190 on a receiving substrate. Thisposition is determined by an electrical signal received by the IC pad orpads 207.

[0071] Integrated circuit 190 may be fabricated into a single block of asemiconductor substrate and then separated from the substrate andfloated into an opening on a receptor substrate to create the structureshown in FIG. 11 (e.g. floated by a fluidic self-assembly process) or itmay be part of a larger conventional integrated circuit which iswire-bonded to a carrier or chip package and attached to a printedcircuit board. However, for the following embodiments which will bedescribed, it will be assumed that the integrated circuit 190 iscontained within a block of a semiconductor which is separated from asemiconductor substrate and then deposited into receptor sites in areceptor substrate through a fluidic self-assembly process.

[0072] The integrated circuit 190 will be deposited onto a receptorsite, such as an opening in a receptor substrate (e.g. see FIG. 11). Theexact position and orientation of the integrated circuit 190 cannot becontrolled in this process. Accordingly, it may be required to determinethe position of the integrated circuit 190 relative to the receptorsubstrate. This requirement may be necessary to determine atranslational position on the substrate (e.g. is the integrated circuitwithin a two-dimensional region or outside of a two-dimensional regionon the receptor substrate) or the rotational orientation of theintegrated circuit on a receptor site on the substrate (e.g. is aparticular connection pad 214 shown in FIG. 6 in the upper left corneror the upper right corner or the lower right corner or the lower leftcorner of the opening on the receptor substrate relative to the positionof interconnect lines on the receptor substrate).

[0073] In one embodiment of the present invention, the translationalposition of the integrated circuit is not detected but the rotationalorientation is detected. In alternative embodiments, however, both maybe detected or merely the translational location may be detected asdescribed below. The position detector 208 receives signals from the pador pads 207 and these signals are decoded to provide a position signalwhich may then be provided to the drivers 200, 201, 202, and 203 throughthe control signal logic 209. Alternatively, the position detector logicmay provide a signal directly to the microcontroller 191 which can thenprovide signals to a control bus 204 to specify the desiredfunctionality based on the position to each of the drivers 200, 201,202, and 203.

[0074] In one particular embodiment (e.g. see FIG. 12) the controlsignal logic 209 provides the signals specifying the position directlyto the drivers 200, 201, 202, and 203. These drivers, after the positionhas been determined by the position detector logic 208, then provideappropriate control signals so that the configurable pads, such as pads196, 197, 198, and 199 can be appropriately configured for the detectedposition. For example, in one embodiment, driver 200 may configure pad196 as an input pad and driver 202 may configure pad 198 as an outputpad allowing data to be, for example, shifted into pad 196 throughdriver 200 and then to the data bus 205 and then to the driver 202 foroutputting of the data through the pad 198. In this case, this wouldprovide for the functionality in which the pixel data is shifted fromleft to right from display driver to display driver. At the same timethe control signals to drivers 201 and 203 would cause the pads 197 and199 to be configured to be no-operation pads. The signals coming intopad 196 would be supplied by the driver 200 directly to pads 192 (fordata intended for those pads) or to the data bus 205 which is used todistribute the data to the other drivers. While a parallel data bus 205is shown in FIG. 12, it will be appreciated that a serial data bus mayalso be utilized as an alternative embodiment.

[0075] The microcontroller 191 may optionally be coupled to the data busto receive data and to store it internally within the microcontroller(e.g. within a register in the microcontroller) which then can be usedto put the data back on the bus and control the control bus 204 to causeanother driver to receive its data under control of the microcontroller191.

[0076] It will be appreciated that the integrated circuit 190, whenfabricated in a block of a semiconductor substrate which is thenseparated from the substrate and deposited through a fluidicself-assembly process onto a receptor substrate, is a case of arotationally symmetric microcontroller or microprocessor. That is, theintegrated circuit 190 includes a microcontroller or microprocessor inan integrated circuit which is externally functionally symmetric. Themicrocontroller or microprocessor may include many of the conventionalcomponents of a microcontroller or a microprocessor such as instructiondecoders, instruction registers, data registers, ALU (arithmetic logicunits), etc. Further, the functionality of this integrated circuit maybe determined by the position detector logic 208 such that in oneembodiment the integrated circuit provides one functionality in oneposition and another functionality in another position. Further, in yetanother embodiment, the configurable pads may be configured to providedifferent signals or functions depending upon the position of theintegrated circuit relative to the receptor substrate.

[0077]FIG. 13 illustrates an exemplary display 500 made according to thepresent invention. The display 500 includes the display substrate 202having an array of transparent conductors 212. The display 500 has apitch P3, which, in this example, ranges from 200 μm to 250 μm. Thepitch of the display however, depends on the desirable resolution of thedisplay. The higher the resolution of the display 500, the smaller thepitch P3 is. The carrier 206 is having a plurality of IC devices 210embedded therein is coupled to the display according to the embodimentsdiscussed above.

[0078] In this example, the IC devices 210 are evenly spaced apart alongthe carrier 400. Interconnections are made from the IC devices 210 tothe array of transparent conductors 212. The interconnections areestablished from at least two sides of the IC devices 210.Interconnections from at least two sides of the IC devices enables thecarrier 500 to have a pitch P2 that is substantially similar to thepitch P3 of the display 500. For example, when the pitch P3 of thedisplay 500 is 200 μm, the carrier 400 has a pitch P2 that is nearlyequal to 200 μm. The IC devices 210 have a pitch P1 that issubstantially similar to the pitch P2. The pitch P1 is alsosubstantially similar to the pitch P3. The pitch P1 may be 150 μm or 250μm and still would be considered substantially similar to the pitch P3of the display.

[0079]FIG. 14 illustrates another exemplary embodiment of the presentinvention. This figure illustrates a display 601. The display 300 issimilar to the display 300 shown in FIG. 7 in that interconnections fromthe IC devices 210 are made from at least two sides of each of the ICdevices 210. The display 601 differs from the display 300 in that the ICdevices 210 are integrated directly into the display substrates. Inparticular, the display 601 comprises of top substrate 602 and a bottomsubstrate 604. These substrates can be made out of a transparentmaterial suitable for making a display. In one example, these substratesare flexible. The top substrate 602 may include a column array oftransparent conductors 606 and the bottom substrate 604 may include arow array of transparent conductors 608. The top substrate 602 furtherincludes a plurality of IC devices 210 integrated into the top substrate602 as opposed to being placed into a carrier like the carrier 400discussed above. The bottom substrate 604 also includes a plurality ofIC devices 210 integrated into the bottom substrate 604. All otheraspects of the display 601 are similar to the display 300 discussedabove.

[0080]FIGS. 15A and 15B illustrate an exemplary display 601 madeaccording to the present invention. The display 601 of these figures issimilar to the display 601 of FIG. 14 except that a double-layerstructure conductor facilitates the interconnection of the IC devices210 to the array of the transparent conductors on the displaysubstrates. Similar to FIG. 14, the display 601 has a plurality of ICdevices 210 that are integrated into the top or the bottom substrate ofthe display 601. A small area along an edge of the substrate 610 isreserved for the IC devices to be integrated into the display 601. Thisarea is referred to as an integration area 622. The substrate 610 can bethe top substrate 602 or the bottom substrate 604 shown in FIG. 14. Inanother embodiment, the IC devices 210 are embedded into a carrier asshown in FIG. 7 and that a double-layer structure conductor is also usedin this embodiment to facilitate the interconnection of the IC devices210 to the array of transparent conductors. In the embodiment where theIC devices 210 are embedded into a carrier which is later coupled to adisplay substrate as discussed above, the substrate 610 of FIGS. 15A and15B is the carrier itself.

[0081]FIG. 15A shows in a cross-sectional view of the integration area622 of the substrate 610 having the IC devices 210 deposited therein. Inthis embodiment, the IC devices 210 drive the display 601 with adouble-layer structure conductor which includes a first set ofconductors 612 and a second set of conductors 614. The first set ofconductors 612 is deposited over the integration area 622 of thesubstrate 610. In one example, the first set of conductors 612 is notdeposited over the IC devices 210. The first set of conductors 612 canbe those conductors that interconnect all of the IC devices in thesubstrate 610 to common electrical inputs to drive the display 601 suchas grounds, signals, data, clock, or power. An insulation layer 620 isdeposited over the entire integration area 622 of the substrate 610which includes the IC devices 210 and the first set of conductors 612.The insulation layer 620 comprises a plurality of contact vias 616formed in the insulation layer 620. The contact vias 616 enable the ICdevices 210 to make interconnections to the first set of conductors 612.The first set of conductors 612 in turn interconnect the IC devices 210to the grounds, signals, data, clock, or power typically needed to drivethe display 601.

[0082] The second set of conductors 614 of FIG. 15A having a patternthat matches the array of the transparent conductors of the substrate610 is deposited over the insulation layer 620. The second set ofconductors 614 interconnects the IC devices 210 to the array oftransparent conductors to drive the pixel images on the display 601. Thesecond set of conductors 614 also interconnects the first set ofconductors 612 to the IC devices. The IC devices thus drive the display601 through the use of a double-layer structure conductor, the first setof conductors 612 and the second set of conductor 614.

[0083]FIG. 15B illustrates another exemplary embodiment the display 601.FIG. 15B shows in a cross-sectional view of the integration area 622 ofthe substrate 610 having the IC devices 210 deposited therein. The ICdevices 210 drive the display 601 with a double-layer structureconductor which includes a first set of conductors 612 and a second setof conductors 614.

[0084] An insulation layer 620 is deposited over the integration area622 of the substrate 610 and over the IC devices 210. The insulationlayer 620 comprises a first plurality of contact vias 616 formed in theinsulation layer 620. The contact vias 616 enable necessary electricalinterconnection from the IC devices 210 to other parts of the display(e.g., the transparent conductors).

[0085] A second set of conductors 614 having a pattern matching thearray of transparent conductors of the display 601 are deposited overthe insulation layer. The second set of conductors 614 controls theinterconnection from the IC devices 210 to the array of transparentconductors to drive the pixel images on the display. The IC devices 210interconnect to the second set of conductors 614 through the contactvias 614. The IC devices 210 are thus able to drive the display throughthese vias.

[0086] A first set of conductors 612 is deposited on the bottom side ofthe integration area 622 of the substrate 610. The first set ofconductors 612 can be those conductors that interconnect all of the ICdevices in the substrate 610 to common electrical inputs to drive thedisplay 601 such as grounds, signals, data, clock, or power. To enableinterconnections from the IC devices 210 to the first set of conductors612, vias are also used. A second plurality of vias 618 formed in theintegration area 622 of the substrate 610 enables the IC devices 210 tointerconnect the first set of conductors 614.

[0087] The IC devices thus drive the display 601 through the use of adouble-layer structure, the first set of conductors 612 and the secondset of conductor 614. These double metal approaches discussed in FIGS.15A and 15B can also be applied to the cases where IC devices are in acarrier, the carrier being interconnected to the display substrate (allFigures prior to FIG. 14).

[0088] FIGS. 16 to 20A, B illustrate further exemplary configurations ofthe double-layer structure conductor discussed in FIG. 15A and 15B. FIG.16 illustrates a topical view an exemplary embodiment of a display 601having the IC devices 210 embedded in a substrate 610. The IC devices210 of this embodiment also drive the display 601 with a double-layerstructure conductor. FIG. 17 illustrates a three-dimensional view of theexemplary display 601 shown in FIG. 16.

[0089] In FIGS. 16 and 17, a substrate 610 is shown to include aplurality of receptor sites 242 each having an IC device 210 depositedtherein. In embodiments where the substrate 610 is a carrier having theIC devices 210 embedded therein, the substrate 610 is similar to thecarriers described above (e.g., carrier 206, carrier 208, and carrier400) described above. The IC device 210 includes a plurality ofconnection pads (illustrated by the black dots) on its surface. Theconnection pads interconnect the active circuits (not shown) within theIC devices 210 to other necessary electrical components to drive thedisplay 601.

[0090] A first set of conductors 612 is deposited over the top surfaceof the substrate 610 FIGS. 16 to 17. The first set of conductors 612 iscoupled to the connection pads on the IC devices 210. The substrate 610of further includes a plurality of vias 618 formed into the substrate610. Each of the first set of conductor 612 goes through a vias 618 toreach the back side of the substrate 610 which further has a second setof conductors 614 deposited thereon. The first set of conductors 612then interconnect the second set of conductors 614. The second set ofconductors 614 has a pattern that matches the array of transparentconductor on the display 601. When all of the interconnections arecomplete, the IC devices drive the display through these first sets ofconductors 612 and the second set of conductors 614. For example, thefirst set of conductors 612 may interconnect with electrical inputs todrive the display 601 such as grounds 624, data signals 626, clock 628,or power 630. And, the second set of conductors 614 may interconnectwith the transparent electrodes (not shown) on the display to drive thepixel images on the display 601.

[0091] The substrate 610 may be attached to the display substrate usingthe ACF tape according to the embodiments described above. In theexample in FIGS. 16 to 17, the ACF tape is deposited over the set ofsecond conductors 614 in an ACF bonding area 615. The ACF tape thenaffixes the substrate 610 to the display substrate (not shown).

[0092]FIGS. 18A and 18B illustrate a top view another exemplaryembodiment of a display 601. The display 601 may have the IC devices 210embedded in a carrier that is coupled to a display panel. Alternativelythe display 601 may have the IC devices 210 integrated directly into thedisplay panel. In both alternatives, the IC devices 210 drive thedisplay 601 with a double-layer structure connector. FIG. 19Aillustrates an exploded three-dimensional view of the exemplaryembodiment shown in FIG. 18. A substrate 610 is shown to include aplurality of receptor sites 242 each having an IC device 210 depositedthere in. The display 601 includes a substrate 610. In the embodimentwhere the IC devices 210 are integrated into the display panel, thesubstrate 610 has an area which extends from the display panel, wherethe IC devices 210 can be integrated. And where the IC devices 210 areembedded into a carrier, the substrate 610 is the carrier which iscoupled to the display panel. The substrate 610 is similar to thecarriers described above (e.g., carrier 206, carrier 208, and carrier400) described above. The IC device 210 includes a plurality ofconnection pads (illustrated by the black dots in FIG. 19A) on itssurface. The connection pads interconnect the active circuits (notshown) within the IC devices 210 to other necessary electricalcomponents to drive the display 601.

[0093] Continuing with FIGS. 18A, 18B, and 19A, a first set ofconductors 612 is deposited on the back surface of the substrate 610.The first set of conductors 612 interconnect the connection pads on theIC devices 210 through a first plurality of vias 618 formed into thesubstrate 610. In one example, each of the first set of conductors 612goes through a vias 618 from the back surface of the substrate 610 toreach the connection pads on the IC devices 210. It is also through thevias 618 that the first set of conductors 612 can also reach a secondset of conductors 614 which is deposited over an insulation layer 620.

[0094] The insulation layer 620 is deposited over the top surface of thesubstrate 610 having the IC devices 210 deposited therein. Theinsulation layer 620 includes a second plurality of vias 616 (FIG. 19A)formed through the insulation layer 620. In one example, the secondplurality of vias 616 are formed over the area that electricalinterconnections are desired.

[0095] A second set of conductors 614 is deposited over the insulationlayer 620 and interconnecting the IC devices 210 through the firstplurality of vias 618 and the second plurality of vias 616. In thisexample, the second set of conductors 614 has a pattern that matches thearray of transparent conductor (not shown) on the display 601. Thesecond set of conductors 614 then interconnect the IC devices 210 to thetransparent electrodes on the display 601 substrate to drive the display601.

[0096] The first set of conductors 612 also interconnect the second setof conductors 614 as illustrate in FIG. 18A. When all of theinterconnections are complete, the IC devices 210 drive the displaythrough the first set of conductors 612 and the second set of conductors614. For example, the first set of conductors 612 may interconnect withelectrical inputs to drive the display 601 such as grounds 624, datasignals 626, clock 628, or power 630. The first set of conductors 612may also interconnect one IC device 210 to another IC device 210 withinthe substrate 610. For example, the conductor 631 interconnects two ICdevices 210 to each other as shown in FIG. 19A. The first set ofconductors 612 interconnect with the second set of conductors 614 todeliver the electrical inputs (e.g., grounds 624, data signals 626,clock 628, or power 630) to the IC devices 210 which in turn drive thedisplay 601.

[0097]FIG. 19B illustrates another embodiment. In some cases, theinsulation layer 620 may need to be deposited directly above thesubstrate 610 to secure the IC devices 210 in the Receptor sites 242 inthe substrate 610. In this embodiment, the first set of conductors 612deposited on the bottom of the substrate 610 does not contact the ICdevices 210 directly. Instead, the first set of conductors 612interconnect the IC devices 210 through the first set of plurality ofvias 618 formed through the substrate 610. The first set of conductors612 may interconnect with conducting pads 614(a) which in turninterconnects the first set of conductors 612 to the IC devices 210 asshown in FIG. 19B. The IC devices 210 may interconnect the array oftransparent conductors on the display panel (not shown) through thesecond set of conductors 614(b). The second set of conductors 614(b) mayhave a pattern that matches the pattern of the array of transparentconductors.

[0098] In the embodiments where the substrate 610 is a carrier, thesubstrate 610 in the embodiments described above may be attached to thedisplay panel using the ACF tape described above. In this example, anACF tape is deposited over the set of second conductors 614 over the ACFbonding area 615. The ACF tape then affix the substrate 610 to thedisplay 601 according conventional methods.

[0099]FIGS. 20A and 20B illustrate another exemplary embodiment of adisplay 601 having the IC devices embedded in a substrate 610 (ordirectly incorporated in the display substrate) wherein the IC devices210 drive the display 601 with a double-layer structure conductor. FIG.20A is a topical surface illustration and FIG. 20B is a cross-sectionalillustration of FIG. 20A for clarity sake. In this embodiment, thesubstrate 610 (or the display substrate where the IC devices aredirectly incorporated) is a carrier similar to the carriers 226, 228,and 400 described above wherein the substrate 610 is affixed to adisplay substrate (not shown). The substrate 610 has a plurality of ICdevices 210 deposited therein. This embodiment is similar to theembodiment described in FIGS. 18A, 18B and 19A, and 19B above with oneexception that a first set of conductors is deposited on the top surfaceof a substrate 610 instead of on the bottom of the substrate 610.

[0100] A first set of conductors 612 is deposited on the substrate 610as shown in FIG. 20B. In one example, the first set of conductors 612 isnot deposited over the IC devices 210. The first set of conductors 612may contact the IC devices 210 directly through a plurality ofcontacting pads (not shown here) on the surface of the IC devices 210.The first set of conductors 612 may interconnect the IC devices toelectrical inputs such as ground 624, signal data 626, clock 628 orpower 630 which drive the display.

[0101] An insulation layer 620 is then deposited over the first set ofconductors 612 and the substrate 610 which has the IC devices 210deposited therein. The insulation layer 620 comprises a plurality ofvias (not shown) formed in the insulation layer 620. The contact viasenable the first set of conductors 612 to interconnect a second set ofconductors 614 which is deposited over the insulation layer 620.

[0102] The second set of conductors 614 has a pattern that matches thearray of the transparent conductors of the display substrate. The secondset of conductors 614 interconnects the IC devices (through the vias) tothe array of transparent conductors to drive the pixel images on thedisplay. The IC devices thus drive the display 601 through the use of adouble-layer structure, the first set of conductors 612 and the secondset of conductor 614.

[0103]FIGS. 21A, 21B, and 21C, illustrate yet another embodiment of thepresent invention. In this embodiment, the row and column drivers areincorporated into one substrate of the display. Similar to discussedabove, a display 2000 may comprise of a bottom substrate 2100, whichfurther comprises an array of columns of transparent electrodes 2102 anda top substrate 2200, which further comprises an array of rows oftransparent electrodes 2202.

[0104]FIG. 21A shows that the bottom substrate 2100 has a plurality ofcolumn drivers 2104 (e.g., IC devices 210) interconnect (not shown) tothe array of columns of transparent electrodes 2102 to drive thisportion of the display 2000. The bottom substrate 2100 also has aplurality of row drivers 2105 which are dedicated to driver the array ofrows of transparent electrodes 2202 of the display 2000. This isaccomplished by the bottom substrate 2100 having a plurality ofcross-over connectors 2106 deposited on a contact area 2101. The contactarea 2101 can be an extension from the bottom substrate 2100.Alternatively, the contact area 2101 can be a different piece ofsubstrate that is coupled to or deposited onto the bottom substrate2100. The cross-over connectors 2106 are interconnected to the pluralityof row drivers 2105. The cross-over connectors 2106 have the pattern ofthe array of the rows of transparent electrodes 2202 and are allowed tocontact the array of the rows of transparent electrodes 2202. One way toallow for this contact is using the ACF tape discussed above. Other waysof interconnecting includes dots of conductive epoxy or low-temperaturesolder or other standard interconnect methods. As shown in FIG. 21B, theACF tape 2204 is deposited over a section of the top substrate 2200.When the top substrate 2200 is adhered to the bottom substrate 2100, theACF tape 2204 establishes both electrical and mechanical contacts of thearray of the rows of transparent electrodes 2202 to the cross-overconnectors 2106.

[0105]FIG. 21C illustrates a cross-sectional view of the display 2000having the top substrate 2200 adhered to the bottom substrate 2100. TheACF tape 2204 facilitates the row drivers incorporated in the bottomsubstrate 2100 to drive the rows of transparent electrodes 2202 in thetop substrate 2200. A conventional sealant 2206 such as epoxy can beused according to well known methods to further hold the top substrate2200 and the bottom substrate 2100 together.

[0106] In yet another embodiment, the drivers are incorporated into onecarrier which can be attached to either a top substrate or a bottomsubstrate of a display. All aspects of this embodiment are similar tothe display 2000 described in FIGS. 21A, 21B and 21C. An exemplaryconfiguration of a display having the row and column driversincorporated into a carrier which is attached to the bottom substrate isillustrated in FIG. 22A and 22B. A display 2300 is shown to comprise abottom substrate 2301, a top substrate 2303 and carrier 2310. The topsubstrate 2303 includes an array of rows of transparent conductors 2302.The bottom substrate 2301 includes an array of columns of transparentconductors 2302. The carrier 2310 includes row drivers 2306 and columndrivers 2305 incorporated therein. The row and column drivers can beNano-blocks or microstructures having integrated circuits to drive thedisplay 2300. The carrier 2310 can be divided to two carrier, oneattached to the long edge and one attached to the short edge of thebottom substrate 2301. Alternatively, and as shown in FIG. 22A, thecarrier 2310 is one piece that has an “L” shape. The carrier 2310 can beattached to the bottom substrate 2301 a shown in FIG. 22A.Alternatively, the carrier 2310 can be attached to the top substrate2300. In FIG. 22A, the carrier is attached to the bottom substrate 2301.There, the bottom substrate 2301 also includes a contact area 2308 whichis similar to the contact area 2101 of FIG. 21A above. The top substrate2303 includes an ACF tape 2304. When the top substrate 2300 is adheredto the bottom substrate 2301, the ACF tape 2304 is disposed over thecontact area 2308. The row drivers 2306, which interconnects with thecontact are 2308, will conduct through the ACT tape 2304 to interconnectthe row drivers 2306 to the array of rows of transparent conductor 2302.

We claim:
 1. A display device comprising: a first array of transparentconductors deposited on a display panel, the first array of transparentconductors having a first pitch defined by a first distance betweenfirst adjacent transparent conductors; a carrier having a plurality ofintegrated circuit (IC) devices disposed therein is coupled to thedisplay panel; and a second array of conductors disposed on theplurality of IC devices, the second array of conductors having a secondpitch defined by a second distance between second adjacent conductorswherein the first pitch and the second pitch are substantially similarand wherein the first array of transparent conductors interconnect thesecond array of conductors.
 2. A display device as in claim 1 whereinthe second array of conductors substantially surrounds a perimeter ofeach of the plurality of the IC devices.
 3. A display device as in claim1 wherein the second array of conductors interconnect the first array oftransparent conductors along at least one edge of the carrier.
 4. Adisplay device as in claim 1 wherein the display device has a firstlength, the carrier has a second length wherein the second length issubstantially similar to the first length.
 5. A display device as inclaim 1 wherein the display is flexible.
 6. A display device as in claim1 wherein the plurality of IC devices are NanoBlocks.
 7. A displaydevice as in claim 1 wherein the carrier is flexible.
 8. A displaydevice comprising: a top substrate having a first array of transparentconductors; a bottom substrate having a second array of transparentconductors; and a first carrier coupling to the top substrate; a secondcarrier coupling to the bottom substrate; wherein each of the firstcarrier and the second carrier includes a plurality of IC devices and aplurality of carrier conducting pads to interconnect the plurality of ICdevices to the first array of transparent conductors and the secondarray of transparent conductors; and wherein each of the plurality of ICdevice has an array of interconnections which substantially surround aperimeter of each of the plurality of IC devices.
 9. A display device asin claim 8 wherein the plurality of carrier conducting pads is alignedalong at least one edge of each of the first carrier and the secondcarrier.
 10. A display device as in claim 8 further comprisingconductive bonding deposits to couple the first carrier to the topsubstrate and the second carrier to the bottom substrate.
 11. A displaydevice as in claim 10 wherein the conductive bonding deposits areanisotropic conductive films.
 12. A display device as in claim 8 whereinthe plurality of carrier conducting pads includes signal inputs andsignal outputs wherein the signal inputs convey first signals to theplurality IC devices and the signal outputs convey second signals fromthe plurality of the IC devices to appropriate conductors of the firstarray of transparent conductors and the second array of transparentconductors.
 13. A display device as in claim 12 wherein the firstsignals include at least one of a power supply signal, a data signal, aclock signal, and a ground signal.
 14. A display device as in claim 8wherein the carrier conducting pads are made out of a conductivematerial.
 15. A display device as in claim 14 wherein the conductivematerial is selected from a group consisting of aluminum, molybdenum,gold, silver, and copper.
 16. A display device as in claim 8 whereineach of the first carrier and the second carrier has a plurality ofreceptor sites each of which is designed to mate with one of theplurality of IC devices.
 17. A display device as in claim 8 wherein eachof the plurality of IC devices is coupled to a receptor site such thatthe plurality of IC devices are embedded below a native surface of thefirst carrier and the second carrier.
 18. A display device as in claim 8wherein the first carrier and the second carrier are flexible.
 19. Adisplay device as in claim 8 wherein the top substrate and the bottomsubstrate are flexible.
 20. A display device as in claim 8 wherein eachof the top substrate and the bottom substrate is made out of one ofplastic and glass.
 21. A display device as in claim 8 wherein theplurality of IC devices includes at least twenty IC devices.
 22. Adisplay device as in claim 8 wherein the display has a first pitchdefined by a first distance between adjacent transparent conductors ofthe first array of transparent conductors and the second array oftransparent conductors and wherein each of the first carrier and thesecond carrier has a second pitch defined by a second distance betweenadjacent interconnections of the plurality of interconnections on eachof the plurality of IC devices wherein the first pitch and the secondpitch are substantially similar.
 23. A display device as in claim 8wherein the plurality of IC devices includes more than two IC devicesthat are identical and evenly spaced along the carrier wherein thedisplay has a first pitch defined by a first distance between adjacenttransparent conductors of the first array of transparent conductors andthe second array of transparent conductors and wherein each of the firstcarrier and the second carrier has a second pitch defined by a seconddistance between adjacent interconnections of the plurality ofinterconnections on each of the plurality of IC devices wherein thefirst pitch and the second pitch are substantially similar.
 24. Adisplay device as in claim 8 wherein the first carrier is coupled to thetop substrate such that a first top surface of the first carrier isbrought into a direct contact with the first array of transparentconductors that extend out from the top substrate and wherein the secondcarrier is coupled to the bottom substrate such that a second topsurface of the second carrier is brought into the direct contact withthe second array of transparent conductors that extend out from thebottom substrate.
 25. A display device as in claim 8 wherein the ICdevices are NanoBlocks.
 26. A display device as in claim 8 wherein thefirst array of transparent conductors and the second array oftransparent conductors are made out of ITO.
 27. A display device as inclaim 8 wherein the top substrate and the bottom substrate have a firstlength and wherein the first carrier and the second carrier have asecond length.
 28. A display device as in claim 8 wherein the secondlength is substantially equal to the first length.
 29. A display deviceas in claim 8 wherein the interconnections further include integratedcircuit conducting pads, the integrated circuit conducting padssubstantially surround a perimeter of each of the plurality of ICdevices and interconnect the plurality of IC devices to the carrierconducting pads.
 30. A display device as in claim 8 further comprising adisplay medium deposited between the top substrate and the bottomsubstrate.
 31. A display device comprising: a top substrate having afirst array of transparent conductors; a bottom substrate having asecond array of transparent conductors; a first plurality of IC devicesand a second plurality of IC devices fabricated onto one of the topsubstrate or the bottom substrate; and a crossover contact area extendedfrom the one of the top substrate and the bottom substrate which has thefirst plurality of IC devices and the second plurality of IC devicesfabricated therein, the crossover contact area includes a plurality ofcontact conductors which interconnect the second plurality of IC devicesto one of the top substrate or the bottom second substrate which doesnot have the first plurality of IC devices and the second plurality ofthe IC devices fabricated therein.
 32. A flat panel display as in claim31 further comprising a conductive bonding deposit disposed over thecrossover contact area, the conductive bonding deposit electricallyinterconnects the second plurality of IC devices to one of the topsubstrate or the bottom substrate which does not have the firstplurality of IC devices and the second plurality of the IC devicesfabricated therein.
 33. A display device as in claim 31 wherein theconductive bonding deposit is an anisotropic conductive film.
 34. Adisplay device as in claim 31 wherein the first set of transparentconductors and the second set of transparent conductors are made out ofITO.
 35. A display device as in claim 31 wherein the top substrate andthe bottom substrate are flexible.
 36. A display device as in claim 31wherein the top substrate and the bottom substrate are made out of oneof plastic and glass.
 37. A display device as in claim 31 wherein eachof the plurality of the IC devices is a NanoBlocks.
 38. A display deviceas in claim 31 wherein each IC device in the first plurality of the ICdevices and in the second first plurality of the IC devices includes aplurality of integrated circuit conducting pads which substantiallysurrounds a perimeter of each of the plurality of the IC devices andwhich establish necessary interconnections from the IC device.
 39. Adisplay device as in claim 38 wherein the necessary interconnectionsinclude interconnections from first plurality of the IC devices to thefirst array of transparent conductors and interconnections from thesecond plurality of the IC devices to the second array of transparentconductors.
 40. A display device as in claim 39 wherein the necessaryinterconnections are made from more than one side of the IC device. 41.A display device as in claim 31 further comprising a display mediumdeposited between the top substrate and the bottom substrate.
 42. Adouble-layer structure conductor for use with a display devicecomprising: a substrate including a plurality of IC devices depositedtherein; a first set of conductors and a second set of conductorsseparated by an insulation layer, the insulation layer has a pluralityof contact vias forming therethrough; a plurality of conducting padslocating on a surface of each of the first plurality of the IC devices,wherein the plurality of conducting pads interconnect with one of thefirst set of conductors and the second set of conductors through theplurality of contact vias; the first set of conductors and the secondset of conductors interconnect with each other through the plurality ofcontact vias; and one of the first set of conductors and the second setof connectors interconnect with an array of transparent conductors inthe display device.
 43. A double-layer structure conductor for use witha display device as in claim 42 wherein the substrate includes a displayarea having the array of transparent conductors deposited therein.
 44. Adouble-layer structure conductor for use with a display device as inclaim 42 wherein the substrate is a carrier coupling to a displaysubstrate having the array of transparent conductors.
 45. A double-layerstructure conductor for use with a display device as in claim 44 furthercomprising a conductive bonding deposit for coupling the carrier to thedisplay substrate having the array of transparent conductors
 46. Adouble-layer structure conductor for use with a display device as inclaim 45 wherein the conductive bonding deposit is an anisotropicconductive film.
 47. A double-layer structure conductor for use with adisplay device as in claim 46 wherein the carrier is coupled to thedisplay substrate such that one of the first set of conductors and thesecond set of conductors on the carrier is in direct contact with thearray of transparent conductors.
 48. A double-layer structure conductorfor use with a display device as in claim 42 wherein first set ofconductors is deposited on the bottom surface of the substrate andwherein the substrate further includes another plurality of contact viaswherethrough the first set of conductors interconnect the second set ofconductors.
 49. A double-layer structure conductor for use with adisplay device as in claim 42 wherein each IC device of the plurality ofIC devices comprises a plurality of integrated circuit conducting padssubstantially surrounding a perimeter of the IC device wherein theplurality of integrated circuit conducting pads facilitatesinterconnections from the IC device to the first set of conductors andthe second set of conductors.
 50. A double-layer structure conductor foruse with a display device as in claim 49 wherein the interconnectionsare made from more than one sides of the IC device.
 51. A display devicecomprising: a top substrate having a first array of transparentconductors; a bottom substrate having a second array of transparentconductors; a carrier having a first plurality of IC devices and asecond plurality of IC devices coupling to one of the top substrate andthe bottom substrate; a crossover contact area extended from the one ofthe top substrate and the bottom substrate which has the carriercoupling thereto, the crossover contact area includes a plurality ofcontact conductors which interconnect the second plurality of IC devicesto one of the top substrate and the bottom second substrate which doesnot have the carrier coupling thereto.
 52. A flat panel display as inclaim 51 further comprising a conductive bonding deposit disposed overthe crossover contact area, the conductive bonding deposit electricallyinterconnects the second plurality of IC devices to one of the topsubstrate and the bottom substrate which does not have the carriercoupling thereto.
 53. A display device as in claim 51 wherein theconductive bonding deposit is an anisotropic conductive film.
 54. Adisplay device as in claim 51 wherein the first set of transparentconductors and the second set of transparent conductors are made out ofITO.
 55. A display device as in claim 51 wherein the top substrate andthe bottom substrate are flexible.
 56. A display device as in claim 51wherein the top substrate and the bottom substrate are made out of oneof plastic and glass.
 57. A display device as in claim 51 wherein eachof the plurality of the IC devices is a NanoBlocks.
 58. A display deviceas in claim 51 wherein each IC device in the first plurality of the ICdevices and in the second first plurality of the IC devices includes aplurality of integrated circuit conducting pads which substantiallysurrounds a perimeter of each of the plurality of the IC devices andwhich establish necessary interconnections from the each IC device. 59.A display device as in claim 58 wherein the necessary interconnectionsinclude interconnections from first plurality of the IC devices to thefirst array of transparent conductors and interconnections from thesecond plurality of the IC devices to the second array of transparentconductors.
 60. A display device as in claim 59 wherein the necessaryinterconnections are made from more than one side of the each IC device.61. A display device as in claim 51 further comprising a display mediumdeposited between the top substrate and the bottom substrate.
 62. Amethod of making a display device comprising: coupling a carrier havinga plurality of integrated circuit (IC) devices disposed therein to adisplay panel, the display panel comprising a first array of transparentconductors having a first pitch defined by a first distance betweenfirst adjacent transparent conductors, the plurality of IC devicescomprising a second array of conductors disposed thereon, the secondarray of conductors having a second pitch defined by a second distancebetween second adjacent conductors, wherein the first pitch and thesecond pitch are substantially similar; and interconnecting the firstarray of transparent conductors to the second array of conductors.
 63. Amethod of making a display device as in claim 62 wherein the secondarray of conductors substantially surrounds a perimeter of each of theplurality of the IC devices.
 64. A method of making a display device asin claim 62 wherein the second array of conductors interconnect thefirst array of transparent conductors along at least one edge of thecarrier.
 65. A method of making a display device comprising: coupling afirst carrier to a top substrate having a first array of transparentconductors; coupling a second carrier to a bottom substrate having asecond array of transparent conductors; wherein each of the firstcarrier and the second carrier includes a plurality of IC devices and aplurality of carrier conducting pads which interconnects the pluralityof IC devices to the first array of transparent conductors and thesecond array of transparent conductors; and each of the plurality of ICdevice has an array of interconnections which substantially surround aperimeter of each of the plurality of IC devices.
 66. A display deviceas in claim 65 comprising placing the plurality of carrier conductingpads along at least one edge of each of the first carrier and the secondcarrier.
 67. A method of making a display device as in claim 65comprising adhering the first carrier to the top substrate and adheringthe second carrier to the bottom substrate using conductive bondingdeposits.
 68. A method of making a display device as in claim 62comprising depositing a display medium between the top substrate and thebottom substrate.
 69. A method of making a display device comprising:coupling a first plurality of IC devices and a second plurality of ICdevices to a bottom substrate; and forming a crossover contact area inthe bottom substrate, the crossover contact area includes a plurality ofcontact conductors which interconnects the second plurality of ICdevices to a top substrate; wherein the top substrate includes a firstarray of transparent conductors and the bottom substrate includes asecond array of transparent conductors.
 70. A method of making a displaydevice as in claim 69 wherein the crossover contact area is an extensionof the bottom substrate.
 71. A method of making a display devicecomprising: coupling a first plurality of IC devices and a secondplurality of IC devices to a carrier which is coupled to a bottomsubstrate; forming a crossover contact area in the bottom substrate, thecrossover contact area includes a plurality of contact conductors whichinterconnects the second plurality of IC devices to a top substrate;wherein the top substrate includes a first array of transparentconductors and the bottom substrate includes a second array oftransparent conductors.
 72. A method of making a display device as inclaim 71 wherein the crossover contact area is an extension of thebottom substrate.
 73. A flat panel display as in claim 71 furthercomprising disposing a conductive bonding deposit over the crossovercontact area, the conductive bonding deposit electrically interconnectsthe second plurality of IC devices to one of the top substrate and thebottom substrate.
 74. A display device as in claim 71 further comprisingdepositing a display medium between the top substrate and the bottomsubstrate.
 75. A method of making a display device comprising: disposinga first set of conductors and a second set of conductors separated by aninsulation layer on a substrate, the substrate includes a plurality ofIC devices deposited therein, the insulation layer has a plurality ofcontact vias forming therethrough, and each IC devices of the pluralityof IC devices includes a plurality of conducting pads on a surface ofthe IC devices; interconnecting the plurality of conducting pads to oneof the first set of conductors and the second set of conductors throughthe plurality of contact vias; interconnecting the first set ofconductors to the second set of conductors through the plurality ofcontact vias; and interconnecting one of the first set of conductors andthe second set of connectors interconnect to an array of transparentconductors in the display devices.
 76. A method of making a displaydevice as in claim 75 wherein the substrate is a carrier coupling to adisplay substrate having the array of transparent conductors.
 77. Amethod of making a display device as in claim 75 wherein the substrateincludes the array of transparent conductors.